This invention relates in general to logic clock circuits and more particularly to non-overlap clocks.
Non-overlap clock circuits are very important for large scale integrated circuits constructed from MOS devices. Non-overlap clocks are used extensively to prevent glitches in dynamic circuits. One commonly used non-overlap circuit is shown in FIG. 1. As shown in FIG. 1, non-overlap clock circuit 20 comprises two NOR-gates 22, 24 and inverter 26 connected as shown. The output non-overlap clock signals are provided at outputs A, B. The output signal at B follows the input signal Vin. The output signal at A, however, follows Vin in opposite phase. Thus, when Vin goes up node A and node 28 go low following which node B goes high. When Vin goes low, node 28 goes high. This forces node B to go low which in turn causes node A to go high. The non-overlap circuit of FIG. 1 is disadvantageous in that node A goes high after one and one-half pair delay after Vin goes low. Such delay is quite a penalty for obtaining non-overlap clock signals which do not simultaneously exceed a predetermined level.
In U.S. Pat. No. 4,296,339 Murotani discloses an address inverter for producing, in response to a variable address input signal, a first and a second output signal. The first output signal varies with phase opposite to that of the address signal. The second output signal varies in phase with the address signal. The variable address binary signal is applied to a first inverter for inverting the signal and then through a first buffer circuit to produce the first output signal of opposite phase to the input address signal. The input address signal is also applied to a second inverter for inverting the signal and to a second buffer circuit which inverts the signal again to produce the second output signal in phase with the input address signal. The second inverter is made to vary faster than the first inverter. As a result the second output signal follows the input address signal faster than the first inverter so that the second output signal follows the input address signal faster than the first output signal. This prevents the two output signals from simultaneously having levels lower than a predetermined level. In many large scale integrated circuits, however, it is desirable to generate two non-overlap clock signals which are such that both output signals will not simultaneously have levels higher than a predetermined level. Thus, Murotani achieves a result which is opposite to that desired in such large scale integrated circuits.
Gehrig in U.S. Pat. No. 4,045,685 discloses an MOS power stage of a two-stage phase clock circuit generator for reducing power lost. An input square wave signal drives a binary frequency divider stage. The two outputs of the frequency divider controls the gates of two transistors. The MOS power stage comprises one MOSFET inverter. The main current paths of the two transistors are each coupled at one end to the output of the power inverter; the other ends of the transistor main current paths form the two outputs of the power stage. The two-phase clock circuit disclosed by Gehrig, however, produces non-overlap clock signals of frequency equal to half the frequency of the input square wave signal. In many large scale integrated circuit applications it is desirable to provide non-overlap signals with frequency equal to that of an input signal.
It is therefore desirable to provide a non-overlap circuit which provides two non-overlapping output signals with the same frequency as a variable input signal where the rise times of the output signals are not excessively delayed.